instruction prefetch - ορισμός. Τι είναι το instruction prefetch
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Τι (ποιος) είναι instruction prefetch - ορισμός

METHOD OF IMPROVING INSTRUCTION-LEVEL PARALLELISM
Instruction Prefetch Queue; Superpipelined; Deep pipelining; Pipelined CPU; Prefetch instruction queue; Superpipeline; Pipelined processor; Instruction pipeline
  • A bubble in cycle 3 delays execution.

instruction prefetch         
COMPUTER PROCESSING TECHNIQUE TO BOOST MEMORY
Instruction prefetch; Cache Prefetching
<architecture> A technique which attempts to minimise the time a processor spends waiting for instructions to be fetched from memory. Instructions following the one currently being executed are loaded into a prefetch queue when the processor's external bus is otherwise idle. If the processor executes a branch instruction or receives an interrupt then the queue must be flushed and reloaded from the new address. Instruction prefetch is often combined with pipelining in an attempt to keep the pipeline busy. By 1995 most processors used prefetching, e.g. {Motorola 680x0}, Intel 80x86. [First processors using prefetch?] (1998-03-29)
Cache prefetching         
COMPUTER PROCESSING TECHNIQUE TO BOOST MEMORY
Instruction prefetch; Cache Prefetching
Cache prefetching is a technique used by computer processors to boost execution performance by fetching instructions or data from their original storage in slower memory to a faster local memory before it is actually needed (hence the term 'prefetch'). Most modern computer processors have fast and local cache memory in which prefetched data is held until it is required.
superpipelined         
1. Traditional pipelined architectures have a single pipeline stage for each of: instruction fetch, instruction decode, memory read, ALU operation and memory write. A superpipelined processor has a pipeline where each of these logical steps may be subdivided into multiple pipeline stages. 2. Marketese for pipelined.

Βικιπαίδεια

Instruction pipelining

In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.